The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices having electrode pads.
In recent years, in order to reduce parasitic capacitance caused by an increase in density of interconnection to correspond to higher-speed operation of semiconductor devices, low dielectric constant materials having lower dielectric constants than conventional silicon compounds such as silicon oxide films and silicon nitride films have become increasingly used for interlayer insulating films. Lower dielectric constant materials having dielectric constants lower than 3 are significantly differ from conventional oxide film dielectrics in physical characteristics, such as lower Young's modulus, lower hardness, a higher coefficient of thermal expansion and higher moisture absorbency. The difference in the physical characteristics increases with a decrease in the dielectric constant. Thus, in a semiconductor device using a low dielectric constant material, large pressure is applied to an electrode pad in a testing process using a probe etc., and in a process for forming external electrical connection such as wire bonding. This causes a crack in an insulating film underlying the electrode pad and made of a low dielectric constant material. The insulating film absorbs moisture from the crack and diffuses the moisture, thereby degrading reliability of interconnects around the electrode pad.
In particular, in a charge coupled device (CCD) or an image sensor on which a circuit requiring high-speed operation, a chip including an interconnect layer needs to be located low in relation to optical characteristics. In this structure, the above-described problem easily occurs, since the thickness of the insulating film formed in the chip is reduced.
As conventional solution of the problem, there is a method of forming a multilayer of interconnects and vias under an electrode pad to mechanically reinforce the electrode pad structure, thereby reducing cracks. Also, there is a method of surrounding an electrode pad with a ring structure formed by stacking interconnects and line vias, thereby confining moisture inside the ring structure not to diffuse the moisture to the outside of the ring structure, even when a crack occurs in a layer under the electrode pad and the layer absorbs the moisture from the crack (see, e.g., Japanese Patent Publication No. 2005-142553).
FIGS. 21-23 illustrate a conventional semiconductor device having the electrode pad structure surrounded by the ring structure shown in the patent publication. As shown in FIGS. 21-23, an electrode pad structure 100 is formed on a semiconductor substrate 101 made of silicon. The electrode pad structure 100 includes a connecting portion 115 formed of a metal plate and formed on a plurality of insulating films stacked one on another. The stacked insulating films are sequentially formed on a semiconductor substrate 101, and are a first insulating film 102, a second insulating film 104, a third insulating film 107, and a fourth insulating film 111 including liner films 103 therebetween.
In a region below the connecting portion 115, a plurality of first interconnects 120 are formed in the second insulating film 104, a plurality of second interconnects 122 are formed in the third insulating film 107, a third interconnect 124 being a plate is formed in the fourth insulating film 111 to be in contact with the connecting portion 115. A plurality of vias 121 are formed between the first interconnects 120 and the second interconnects 122 to be connected to the first and second interconnects 120 and 122. A plurality of vias 123 are formed between the second interconnects 122 and the third interconnect 124 to be connected to the second and third interconnects 122 and 124. As such, a multilayer 117 including the connecting portion 115 of the electrode pad structure 100 is configured.
The multilayer 117 including the connecting portion 115 is surrounded by a ring body 118. The ring body 118 includes a fourth interconnect 130 formed in the second insulating film 104, a fifth interconnect 132 formed in the third insulating film 107, and a sixth interconnect 134 formed in the fourth insulating film 111. A line via 131 is formed between the fourth interconnect 130 and the fifth interconnect 132 to be connected to the fourth and fifth interconnects 130 and 132. A line via 133 is formed between the fifth interconnect 132 and the sixth interconnect 134 to be linearly connected to the fifth and sixth interconnects 132 and 134.
A first protective insulating film 114 is formed over the ring body 118 and on the fourth insulating film 111. A peripheral portion of the connecting portion 115 is formed on and across a peripheral portion of the first protective insulating film 114. In addition, a second protective insulating film 116 is formed on the first protective insulating film 114 to interpose the peripheral portion of the connecting portion 115 therebetween.
As shown in FIGS. 21 and 23, a lead line 124A electrically connected to an internal circuit is lead out from the electrode pad structure 100. The lead line 124A is a lead-out part of the third interconnect 124 under the connecting portion 115. Thus, a missing part 134a of the sixth interconnect 134 is formed in the part of the ring body 118, in which the lead line 124A is formed.